Sittel, P., Kumm, M., Möller, K., Hardieck, M., Zipf, P. (Hrsg.), 2017. High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. Shaker Verlag, Herzogenrath.

Möller, K., 2017. Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays. kassel university press, Kassel.

Möller, K., Kumm, M., Zipf, P., Müller, C.-F., 2015. Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. FPGAs for Software Programmers 2015, 1–8.

Möller, K., Kumm, M., Barschtipan, B., Zipf, P., 2014. Dynamically Reconfigurable Constant Multiplication on FPGAs, in: Ruf, J., Allmendinger, D., Michel, M. (Hrsg.), Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). Cuvillier Verlag, Göttingen, S. 159–169.

Kumm, M., Klingbeil, H., Möller, K., Zipf, P., Groß, K., Lens, D., 2014. FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons, in: Große, K. (Hrsg.), Scientific Report 2013. GSI Helmholtzzentrum für Schwerionenforschung, Darmstadt, S. 331–332.

Möller, K., Kumm, M., Kleinlein, M., Zipf, P., 2014. Pipelined reconfigurable multiplication with constants on FPGAs, in: IEEE (Hrsg.), Field Programmable Logic and Applications (FPL), 2014 24th International Conference on. IEEE, New York, S. 1–6.

Möller, K., Kumm, M., Zipf, P., 2013. Dynamically reconfigurable FIR filter architectures with fast reconfiguration, in: IEEE (Hrsg.), 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, New York, S. 1–8.

Kumm, M., Fanghänel, D., Möller, K., Zipf, P., Meyer-Baese, U., 2013. FIR filter optimization for video processing on FPGAs. EURASIP Journal on Advances in Signal Processing 2013, 111–46.

Möller, K., Kumm, M., Zipf, P., 2013. Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. Circuits and Systems (ISCAS), 2013 IEEE International Symposium on 2054–2057.

Möller, K., Kumm, M., Zipf, P., 2013. Reconfigurable FIR filter using distributed arithmetic on FPGAs. Circuits and Systems (ISCAS), 2013 IEEE International Symposium on 2058–2061.