Beitrag in einem Tagungsband
On-chip safety system for embedded control applications
Details zur Publikation
Autor(inn)en: | Hayek, A.; Börcsök, J. |
Herausgeber: | Institute of Electrical and Electronics Engineers (IEEE) |
Verlag: | IEEE |
Verlagsort / Veröffentlichungsort: | Piscataway, NJ |
Publikationsjahr: | 2014 |
Seitenbereich: | 315-319 |
Buchtitel: | MELECON 2014 - 17th IEEE Mediterranean Electrotechnical Conference |
ISBN: | 978-1-4799-2337-3 |
DOI-Link der Erstveröffentlichung: |
Zusammenfassung, Abstract
In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.
In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.
